Drew Turner, IBM, has organized an excellent tutorial program. The following
lists the invited tutorial speakers and topics:
·
Tutorial #1: Subhasish Mitra,
·
Tutorial #2: Tibor Grasser,
·
Tutorial #3: Alvin Strong, IBM, " JEDEC Overview,"
·
Tutorial #4: Chadwin Young, SEMATECH, " Measurement Issues for High-k
Technology including NBTI,"
·
Tutorial #5: William Tonti, " eFuse Design and Reliability,"
·
Tutorial #6: Wilfried Haensch, IBM, "Reliability
of 'Future' Devices."
Tutorial speakers are
approachable and available throughout the workshop, one of the benefits of the
friendly, intimate setting.
Who: Subhasish Mitra
Title: Circuit Failure Prediction for Robust System Design in Scaled CMOS
Tentative duration: TDB
Circuit failure prediction predicts the occurrence of a circuit failure
"before" errors actually appear in system data and states. This is in
contrast to classical error detection where a failure is detected after errors
appear in system data and states. Circuit failure prediction is performed
concurrently during system operation or during periodic on-line self-test by
analyzing the data collected by special circuits called "sensors"
inserted at strategic locations inside a chip. This talk demonstrates the
concept of circuit failure prediction, practical implementation of the concept,
and its effectiveness in overcoming major scaled-CMOS reliability challenges
such as early-life failures (also called infant mortality) and aging. The
concept of circuit failure prediction also provides insignts into early-life
failure behaviors that may be used in developing new techniques for screening
early-life failure candidates during production test.
Who: Alvin Strong
Title: JEDEC Overview
Tentative duration: 45min
JEDEC is the leading developer of standards for the solid-state industry.
However for some, there may be a mist about JEDEC that clouds the what JEDEC really is and really does. The intent
of this tutorial is to clarify everyone’s understanding
of the mission of JEDEC, to show the breadth of JEDEC, and to give the
opportunities of service. The focus will be on JEDEC 14.2 since this is
the JEDEC committee that is responsible for Wafer Level Reliability.
Furthermore that focus will be on our most recent standards and those
currently on our agenda including the update to the Foundry Guidelines.
Who: Chadwin Young
Title: Measurement Issues for High-k Technology including NBTI
Tentative duration: 1hr 30min
This tutorial will be comprised of several parts that address
various measurement methodologies required for properly characterizing high-k
gate stacks. While discussing these techniques, emphasis will be placed
on proper instrumentation and set up, followed by proper data analysis and
interpretation. Some of the key methodologies that will be discussed are:
Capacitance – Voltage (C-V), Pulsed Current – Voltage (I-V), and
reliability evaluation techniques. The intended outcome of this tutorial is for
the attendees to leave with a better understanding of high-k characterization
requirements that he/she can implement in everyday measurements and have
increased insight about these novel gate stacks.
Who: William R. Tonti
Title: eFuse Design and Reliability
Tentative duration: 1hr 30min
Programmable eFuse designs present an integration challenge in modern CMOS
processing. The power level to program a fuse, and the programming
methodologies leverage reliability mechanisms which all other elements in a
design avoid. A high degree of eFuse process control and circuit design
is required in order to guarantee operation. Almost all eFuse types are
one time programmable and are limited to “one chance” programmable. This
paper will discuss selected eFuse technologies describing the design philosophy,
electrical programming and characterization, the physics of failure, and some
of the many applications an on chip programmable element provides.