IIRW 2006 Keynote

 

Reliability Challenges: Preventing Them from Becoming Limiters to Technology Scaling

 

Jose Antonio Maiz

Intel Fellow, Technology and Manufacturing Group
Director, Logic Technology Quality & Reliability
Intel Corporation

 

 

 

Abstract

 

Aggressive technology scaling continues as projected by Moore’s Law and has not shown signs of slowing down to date. The International Technology Roadmap for Semiconductors (ITRS) projects major challenges for the coming decade including the very real possibility that, along with power, reliability may become a limiter.  Fundamental changes in key materials, transistor architectures, and interconnects are compounded by interactions with design, changes in computing architecture, and the exploration of exotic technologies as potential replacements/ complements to the very successful planar CMOS transistor.

 

In this address, an analysis of the key technology trends relevant to reliability as well as key reliability trends with a potential to slow down technology scaling will be discussed along with key concerns for some of the proposed exotic options.  This analysis will allow an exploration of the options, opportunities for research, and directions that will contribute to removing reliability as a limiter or, at a minimum, to minimize its impact. 

 

 

Biography

 

Jose Maiz is an Intel Fellow and Director of Logic Technology Quality and Reliability.  He joined Intel in 1983, and became Fellow in 2002.  Since he first joined Intel's 1 Mbit DRAM program, he has participated in the development and reliability characterization of over 10 logic technology generations in various individual contributor and management capacities.  He is presently responsible for identification of silicon reliability limiters to scaling and their resolution for Intel's next generation silicon technologies and logic products.  Maiz holds a B.Sc. in physics from the University of Navarra in San Sebastian Spain, and a MSc. and Ph.D degrees in Electrical Engineering from the Ohio State University in 1980 and 1983 respectively. He holds 7 patents and has 5 more pending, has authored or co-authored over 30 publications and conference presentations, a number of them invited, and most recently has co-edited the special TDMR issue on Soft Errors.