IRW 2005 TUTORIALS

         

Intrinsic Limitations on the Performance and Reliability of High-k Gate Dielectrics for Advanced Electronic Devices

Gerry Lucovsky, NC State

 

Three different types of high-k thin film oxides have been considered as alternative/replacement gate dielectrics for advanced Si devices for CMOS applications. These are: i) elemental transition metal/trivalent lanthanide rare earth oxides, with the leading candidate being HfO₂, ii) transition metal silicate and aluminate alloys, with the leading candidate being nitrided Hf silicates, and iii) transition metal/rare earth complex oxides, with one of the leading candidates being La aluminate, LaAlO₃. Each of these high-oxide dielectrics is qualitatively different than thermally-grown SiO₂ and/or Si oxynitride alloys that are currently integrated into state of the art CMOS devices, and integrated circuits. This tutorial will address fundamental differences between i) the electronic structure of band edge states in these three different classes of high-k dielectrics with respect to the corresponding band edge states in SiO₂ and Si oxynitride alloys, and ii) thin film stability as it relates to chemical phase separation and/or crystallization of the transition metal silicate and nitrided silicate alloys that occurs at the temperatures required for process integration of CMOS devices and integrated circuits/systems. The intrinsic properties of the candidate high-k alternative gate dielectrics identified above impact primarily on device performance, but are also important with respect to i) process integration, including latitude and yield, and ii) accelerated device testing for projecting device lifetimes, as for example the projected time to device and circuit breakdown and failure.  

 

Flash Memory Reliability

Alberto Modelli and Angelo Visconti, ST Microelectronics (top)

 

Memory reliability is a key issue of flash technology. The continuous trend to increase the storage density is driving the technology close to its physical limits and new reliability challenges are met.

The tutorial will discuss the failure mechanisms limiting memory endurance and data retention. Reference will be done to the two mainstream flash technologies, considering a floating-gate cell in a NOR- or NAND-type memory array.

 

The first part of the tutorial is dedicated to failure modes related to the intrinsic cell behavior. Classical data loss mechanisms and the degradation of the oxide properties caused by high-field tunneling or channel hot electron injection will be examined. The second part deals with single-cell failures, in particular low-temperature data loss after program/erase cycling, which can be ascribed to tunnel oxide defects. The nature of the leakage current and its relation with the Stress-Induced Leakage Current observed in large area capacitors will be discussed. Design solutions to solve, or at least ease, this issue will be considered.

 

A Survey of Product Reliability in 90nm CMOS and Beyond

Andrew Turner, IBM (top)

 

While 90nm and 45nm CMOS matures from the lab to the manufacturing floor, the reliability of the product becomes more important as defect densities and degradation mechanisms that affect microprocessors may not be observable in sufficient quantities or magnitude at the macro level. There is a need to understand that the interaction between design and manufacturing, as it relates to field reliability, is moving beyond test-site measurements and design simulation alone.

 

Understanding the product reliability and performance metrics through the useful life of the product is imperative. This often requires knowledge of the most sensitive circuits and the mechanisms that are most likely to negatively affect them. Tracking these metrics through an accelerated life stress and evaluating fails is the best bet for successful product qualification.

 

Designing Radiation Hardened CMOS Microelectronic Components at Commercial Foundries: Space and Terrestrial Radiation Environments and Device and Circuit Techniques to Mitigate Radiation Effects

Ron Lacoe, Aerospace Corp. (top)

 

When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part.  Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes.  The approach is often refereed to as hardening-by-process.  However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore’s, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the-art CMOS.  Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed.  In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques.  This presentation will begin with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies.  This will include a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects.  Specific non-standard transistor topologies and the application of guardbands to mitigate total dose effects will be discussed.  Circuit approaches to mitigating single-event effects will also be presented.  The application of these design approaches does not come without area and performance penalties, which will be quantified as part of this presentation.  Unique reliability issues associated with the application of hardness-by-design methodologies will also be discussed.  Finally, a discussion on mitigating terrestrial radiation effects will be presented.

 

MEMS Reliability

Danelle Tanner, Sandia National Labs (top)

 

The main thrust in any reliability work is identifying failure modes and mechanisms.  This is especially true for the new technology of MicroElectroMechanical Systems (MEMS).  This tutorial will include a brief review of MEMS fabrication methods and identify some commercial products.  We describe some of the methods developed to measure materials parameters and surface properties to characterize MEMS devices.  Our reliability methodology employs statistical characterization and testing to help us identify dominant failure modes.  We strive to determine the root cause of each failure mode and to gain a fundamental (science-based) understanding of that mechanism.  The development of predictive models follows from this science-based understanding.  A reliability model for wear in a MEMS application with contacting surfaces is presented. 

 

Design-in Reliability with Emphasis on NBTI

Chittoor Parthasarathy, ST Alliance (top)

 

The advent of NBTI (Negative Bias Temperature Instability) as a prominent degradation mechanism and a host of other factors - diverse offerings from a technology node, complex products and aggressive performance targets - are prompting efforts to develop methodology to analyze device degradation atcircuit/design level with a view to preempt problems later on.   The aim of

this tutorial is to elaborate this "Design-in Reliability" (DiR) methodology applied to CMOS circuits.  In the past, DiR has mainly addressed degradation due to hot-carrier injection (HCI).  In this tutorial, we shall focus on tackling NBTI degradation, individually as well as in conjunction with HCI.

 

We shall begin by reviewing recent developments in understanding NBTI and HCI phenomena and shall discuss implementations of degradation models for SPICE.  Subsequently, we shall look into the aspect of reliability simulation - methods of degradation analysis applied during circuit simulation. In the final section, we shall address the aspect of reliability analysis for different classes of designs from a designer viewpoint: (a) role of operating conditions, modes and stimuli, (b) minimizing the effects of degradation and (c) correlation of predicted results with silicon.  The tone in general shall be to highlight open issues and explore their solutions. We shall conclude by pondering on how the DiR methodology is set to evolve in the future.

 

Reliability Engineering Tools: Bootstrapping and Extreme Value Statistics

Larry Stout, Idaho State Univ. (top)

 

This tutorial will provide practical information on two techniques that are of use to anyone doing statistical data analysis and making statistical inferences. 

 

Reliability engineers often base their decisions on fitting lifetime data to a particular type of distribution (e.g. lognormal, exponential, Weibull).  Statistical bootstrapping is a tool that allows us to explore data and make useful inferences (e.g. mean, confidence intervals) about it without the need for assuming that the data is from a particular underlying distribution. 

 

Bootstrapping was introduced in the late 1970’s and is a computationally intensive Monte-Carlo procedure that is simple to understand and implement.  To bootstrap a statistic (e.g. the sample mean), we draw for example 1000 random resamples with replacement from the original sample data, calculate the statistic of interest (sample mean) for each resample, then estimate the overall sample mean by taking the average of all the 1000 resampled means.  Inferences about our statistic can then be made by inspecting the resulting bootstrap distribution of our 1000 resampled values of the statistic of interest. 

           

The key idea here is that the bootstrap distribution approximates the sampling distribution of the statistic and we use it as a way to estimate the variation in a statistic based on the original data.

 

The second topic of discussion in this tutorial will be an introduction to extreme value statistics.  Extreme values statistics have proven useful in ocean engineering (e.g. highest wave height), meteorology (highest amount of rainfall, maximum wind speed), and in investigating fatigue strength and corrosion.  Here the focus is on the extremes of a measured parameter instead of the typical focus on centralized tendencies such as the mean or median.  I believe that they could also prove useful in exploring electrical reliability issues such as the highest (lowest) use temperature for a metal line, maximum use current flow through a specific device, or the highest use voltage across a capacitor.

 

Back End Reliability

Glenn Alers, Novellus Systems (top)

 

As interconnects become responsible for a larger portion of signal delays in advanced circuits the pressure for aggressive scaling will increase. Current densities will increase as dimensions are reduced and stress management will be more critical as the compliance of low-k materials decreases. However, reducing the interconnect dimensions tend to degrade reliability as the critical volume associated with a failure decreases. This talk will review the conflicting requirements for reliability and product performance and the solutions that are being pursued. Several paths are available for improving electromigration including advanced barriers, copper alloy seed layers and metallic cap layers. However, each of these solutions will come at the cost of line resistance, which is already increasing due to increased scattering in small geometries. Stress migration will become a larger concern at small dimensions because both the absolute stress level and stress gradients will increase at smaller geometries. Reducing the density of the inter-level dielectric will exaggerate these problems due to intrinsically lower adhesion energies and an increased diffusivity of copper, water and ammines in the dielectric. Ultimately, it will be reliability that limits the scaling of interconnects for future nodes.

 

From Micro Breakdown to Hard Breakdown - from Artifact to Destructive Failure?

Robin Degraeve, IMEC (top)

 

Hard breakdown, analog and digital soft breakdown, micro breakdown, progressive breakdown, stress-induced leakage current, anomalous stress-induced leakage current, etc... When a constant voltage stress is applied to a thin (<10 nm) oxide layer many degradation phenomena are observed. All of these have in common that they are localized stress-induced leakage paths involving electrical trap centers in the bulk of the oxide, but different names are in use depending on the magnitude of the leakage current or on the application where they are typically measured. Some of these stress-induced leakage paths can be negligible artifacts for one application while they are showstoppers for another application. This tutorial aims at presenting a comprehensive overview of all these dielectric breakdown phenomena, explaining their origin and showing what test methods and structures are needed to observe and study them. Examples will be presented on SiO₂, SiON and some high-k dielectrics.

 

For more details, please contact our Tutorial Chair, Sylvie Bruyere.