MONDAY, October 20

1:00 – 6:00 p.m. Registration: Pick up badges & handout (Dining Room Lounge). Please lunch before arriving. (No lunch will be served at the camp.)

1:00 – 8:00 p.m. Lodge check-in: Get room assignment, room key, information, and map of lodge area.
If physically challenged, please notify desk of special needs.
1:30 – 3:30 p.m. Tutorial #1: "Theory and application of non-contact methods for in-line reliability determination" by John D'Amico, Semiconductor Diagnostics, Inc.

3:30 – 4:00 p.m. Break

4:00 – 6:00 p.m. Tutorial #2: "Fast wafer level reliability monitoring of product wafers" by Andreas Martin, Infineon Technologies

6:00 – 7:30 p.m. DINNER, (Dining Room) Introduction of workshop agenda; dine with your session chair

7:30 – 8:30 p.m. Tutorial # 3: "MRAM and reliability" by Brian Hughes, Infineon Technologies

8:30 – 9:00 p.m. Discussion Group Assignments/SIG signup (Dining Room Lounge); Poster Preparation (Old Lodge)

9:00 – 10:30 p.m. Mixer & Poster Session 1, (Cathedral Room)

TUESDAY, October 21

7:00 – 8:00 a.m. Breakfast (Dining Room)

8:15 – 8:30 a.m. Welcome & Introduction: Gennadi Bersuker, General Chair. Program Overview: Alvin W. Strong, Tech. Prog. Chair (Angora Rm.)

8:30 – 9:30 a.m. Keynote: "The complete metrology roadmap" by Alain C. Diebold, International SEMATECH

9:30 – 9:45 a.m. Break

9:45 – 11:25 a.m. Session #1: Gate Dielectrics –  SiO₂

1.1. Interface traps and oxide traps creation under NBTI and PBTI in advanced CMOS technology with a 2 nm gate-oxide— M. Denais, STMicroelectronics/L2MP-ISEM, V. Huard, Philips Semiconductors, C. Parthasarathy, STMicroelectronics, G. Ribes, STMicroelectronics/IMEP/ENSERG, F. Perrier, Philips Semiconductors, N. Revil, STMicroelectronics, and A. Bravaix, L2MP-ISEM

1.2. Non-invasive nature of corona charging on thermal Si/SiO₂ structures—M. Dautrich, P.M. Lenahan, A.Y. Kang, Penn State University, and J.F. Conley, Jr., Sharp Labs of America

1.3. Gate oxide reliability parameters in the range 1.6 to 10 nm—R.-P. Vollertsen, Infineon Technologies AG and E.Y. Wu, IBM Microelectronics

1.4. PMOS NBTI-induced circuit mismatch in advanced technologies—M. Agostinelli, S. Lau, S. Pae, P. Marzolf, H.S. Muthali and S. Jacobs, Intel Corporation

11:25 – 12:00 p.m. Group Picture

12:00 – 1:30 p.m. Lunch, Dining Room

1:30 – 3:30 p.m. Tutorial 4: "Reliability physics and chemistry of thin and high-k gate oxides" by Pat Lenahan, Penn State University

3:30 – 4:00 p.m. Break

4:00 – 5:15 p.m. Session #2: Gate Dielectrics – High-K

2.1. Stress test and characterization of high-k thin films—W. Luo, D. Sunard, Y. Kuo, W. Kuo, Texas A&M University

2.2. Reliability concerns for HfO₂/Si devices: dielectric electron traps—A.Y. Kang, P.M. Lenahan, Penn State University, J.F. Conley, Jr., and Y. Ono, Sharp Labs of America

2.3. Charge trapping in MOCVD hafnium-based gate dielectric stack structures and the impact on device performance— C.D. Young, G. Bersuker, G.A. Brown, C. Lim, P. Lysaght, P. Zeitzoff, R.W. Murto, and H.R. Huff, International SEMATECH

2.4. Product specific sub-micron E-Fuse reliability and design qualification—W.R. Tonti, J.A. Fifield, J. Higgins, W. Guthrie, W. Berry, C. Narayan, IBM

6:00 – 7:30 p.m. DINNER, Dining Room

7:30 – 9:00 p.m. Poster Session 2

9:00 – 9:45 p.m. Discussion Groups,: Chair: Sylvie Bruyere, STMicroelectronics (45 minute parallel sessions for each topic)
Attendees are to participate in one of the groups

9:45 – 10:30 p.m. Individual SIG Meetings (to be announced at camp)

WEDNESDAY, October 22

7:00 – 8:00 a.m. Breakfast (Dinning Room)

8:00 – 8:10 a.m. Announcements, (Angora Room)

8:10 – 10:15 a.m. Session #3: bip

3.1. Projecting the reliability of SiGe NPN transistors after AC Ube reverse stress from DC device lifetime—K. Hofmann, Infineon Technologies AG

3.2. A current mirror method for thermal instability of SOI BJT—J. Kim, Y. Liu, and J.A De Santis, National Semiconductor Corporation

3.3. DC and AC hot-carrier characteristics of ultra-thin DPN gate dielectric on partially depleted SOI MOSFETs—E. Zhao, J. Chan, J. Zhang, A.P. Marathe, and K.O. Taylor, AMD

3.4. Performance-reliability trade-offs in high speed Si-Ge BiCMOS—B. O'Connell, P. Chaparala, and B. Mehrotra, National Semiconductor Corporation

3.5. Breakdown walk-in a new PMOS failure mode in high power BiCMOS applications—D.J. Brisbin, A. Strachan, and P. Chaparala, National Semiconductor Corporation

10:15 – 10:45 a.m. Break

10:45 – 12:00 p.m. Session #4: Circuits

4.1. Using time-dependent reliability fallout as a function of yield to optimize burn-in time for a 130 nm SRAM device— K.R. Forbes and N. Arguello, Motorola Semiconductor Product Sector

4.2. Leakage current recovery in SRAM after AC stressing—C. Payan, S. Kumar, A. Thupil, Cypress Semiconductor, S. Kasichainula, Extreme Networks, and W.B. Knowlton, Boise State University

4.3. Effects of circuit-level stress on inverter performance and MOSFET characteristics—N. Stutzke, B.J. Cheek, M. Wiscombe, T. Lowman, Boise State University, S. Kumar, Cypress Semiconductor, R.J. Baker, A.J. Moll, and W.B. Knowlton, Boise State University

12:00 – 1:30 p.m. LUNCH, (Dining Room — Take out Lunch bags available)

1:30 – 6:00 p.m. Open: The afternoon is free for discussion, hiking & other recreation; or for viewing videos shown in parallel:

• Oxide wearout/breakdown/reliability (Angora Room)
  
• MEMS performance and reliability (Cathedral Room)
• Accelerated stress testing (TBA)

6:00 – 7:30 p.m. DINNER, (Dining Room)

7:30 – 9:00 p.m. Discussion Groups,: Chair: Sylvie Bruyere, STMicroelectronics (90 minute parallel sessions for each topic)
9:00 – 10:30 p.m. Individual SIG Meetings

THURSDAY, October 23

7:00 – 8:00 a.m. Breakfast (Dining Room)

8:15 – 8:30 a.m. Announcements, (Angora Room)

8:30 – 10:10 a.m. Session 5 Interconnect/Memory

5.1. Physically-based simulation of the early and long-term failures in the copper dual-damascene interconnect— V. Sukharev, R. Choudhury, and C.W. Park, LSI Logic Corporation

5.2. Dielectric reliability studies of Metal Insulator Metal Capacitors (MIMCAP) with SiN dielectric under unipolar to bipolar AC-stress—R. Schwab and K.H. Allers, Infineon Technologies AG

5.3. A reliability evaluation methodology for memory chips for space applications when sample size is small—Y. Chen, D. Nguyen, S. Guertin, Jet Propulsion Lab, J. Bernstein, University of Maryland, M. White, R. Menke, and S. Kayali, Jet Propulsion Lab

5.4. Improvement of write/erase cycling of memory cells with SiO₂/HfO₂ tunnel dielectric—P. Blomme, B. Govoreanu, IMEC/KULeuven, J. Van Houdt, IMEC, and K. De Meyer, IMEC/KULeuven,

10:10 – 10:40 a.m. Break

10:40 – 11:40 p.m. Wrap-Up

11:45 – 1:15 p.m. LUNCH, (Dining Room)—Leave the Stanford Sierra Camp unless attending JC14.2

2:00 p.m. JEDEC 14.2 Committee on Wafer Level Reliability Meeting